The present invention generally relates to data processing systems, and more particularly relates to a method for interconnecting a central processing unit, a memory unit and a plurality of input/output control units in a system by way of a single common bus.
In a data processing system, particularly in a small-scale data processing system of the prior art, a central processing unit, a memory unit and a plurality of input/output control units are interconnected by way of a common bus, wherein information is transferred by way of the common bus. This common bus consists of a data channel, an address channel, a control channel, a tag channel, an interlock channel and a scanning control channel, wherein the control channel is provided with a data line used for indicating the transmission of the data, and, further, wherein the interlock channel is provided with a "service in" line. When a write operation is required, a master unit provides both the address information and the write information, and at the same time, the master unit changes the state of the data line (in the control channel) to the logic 1. After this step, the master unit changes the state of the "service in" line (in the interlock channel) to the logic 1, and then the write operation begins. While, when a read operation is required, a master unit provides the address information, and at the same time, the master unit changes the state of the data line to the logic 0. After this, the master unit changes the state of the "service in" line to the logic 1 and keeps the same state, during which the read operation is being conducted.
In the above-mentioned data processing system of the prior art, since either the write operation or the read operation is selectively conducted in accordance with the state of the data line, that is, the logic 1 or the logic 0, respectively, if an error occurs in the data line, it will then be impossible to conduct both the write operation and the read operation correctly. This is one of the defects of the prior art. Further, this kind of error often occurs in the data line. This is because, in the data processing system of the prior art, the so-called bus busy signal is individually provided by each of the input/output control units after one of the corresponding input/output control units has requested to occupy the common bus for carrying out the write operation or for carrying out the read operation and after such occupation of the common bus is realized.